Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.Comment: 45 pages, 30 figures, submitted to JINS

Serial powering: Proof of principle demonstration of a scheme for the operation of a large pixel detector at the LHC

Large detectors in high-energy physics experiments are mostly built from many identical individual building blocks, called modules, which possess individual parts of the services. The modules are usually also powered by parallel power lines such that they can be individually operated. The main disadvantage of such a parallel powering scheme is the vast amount of necessary power cables which constitutes also a large amount of material in the path of the particles to be detected. For the LHC experiments already now this is a major problem for the optimal performance of the detectors and it has become evident, that for an upgrade programme alternative powering schemes must be investigated. We prove and demonstrate here for the example of the large scale pixel detector of ATLAS that Serial Powering of pixel modules is a viable alternative. A powering scheme using dedicated voltage regulators and modified flex hybrid circuits has been devised and implemented for ATLAS pixel modules. The modules have been intensively tested in the lab and in test beams and have been compared to those powered in parallel with respect to noise and threshold stability performance. Finally, the equivalent of a pixel ladder consisting of six serially powered pixel modules with about 0.3Mpixels has been built and the performance with respect to operation failures has been studied

Tracking efficiency and charge sharing of 3D silicon sensors at different angles in a 1.4 T magnetic field

A 3D silicon sensor fabricated at Stanford with electrodes penetrating throughout the entire silicon wafer and with active edges was tested in a 1.4 T magnetic field with a 180 GeV/c pion beam at the CERN SPS in May 2009. The device under test was bump-bonded to the ATLAS pixel FE-I3 readout electronics chip. Three readout electrodes were used to cover the 400 pm long pixel side, this resulting in a p-n inter-electrode distance of similar to 71 mu m. Its behavior was confronted with a planar sensor of the type presently installed in the ATLAS inner tracker. Time over threshold, charge sharing and tracking efficiency data were collected at zero and 15 angles with and without magnetic field. The latest is the angular configuration expected for the modules of the Insertable B-Layer (IBL) currently under study for the LHC phase 1 upgrade expected in 2014. (C) 2010 Elsevier B.V. All rights reserved

A measurement of Lorentz angle and spatial resolution of radiation hard silicon pixel sensors

Silicon pixel sensors developed by the ATLAS collaboration to meet LHC requirements and to withstand hadronic irradiation to fluences of up to 1015 neq/cm2 have been evaluated using a test beam facility at CERN providing a magnetic field. The Lorentz angle was measured and found to alter from 9.0\ub0 before irradiation, when the detectors operated at 150 V bias at B = 1.48 T, to 3.1\ub0 after irradiation and operating at 600 V bias at 1.01 T. In addition to the effect due to magnetic field variation, this change is explained by the variation of the electric field inside the detectors arising from the different bias conditions. The depletion depths of irradiated sensors at various bias voltages were also measured. At 600 V bias 280 \u3bcm thick sensors depleted to 48200 \u3bcm after irradiation at the design fluence of 1 7 1015 1 MeV neq/cm2 and were almost fully depleted at a fluence of 0.5 7 1015 1 MeV neq/cm2. The spatial resolution was measured for angles of incidence between 0\ub0 and 30\ub0. The optimal value was found to be better than 5.3 \u3bcm before irradiation and 7.4 \u3bcm after irradiation. \ua9 2002 Elsevier Science B.V. All rights reserved

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC

The CERN RD53 collaboration was founded to tackle the extraordinary challenges associated with the design of pixel readout chips for the innermost layers of particle trackers at future high energy physics experiments. Around 20 institutions are involved in the collaboration, which has the support of both ATLAS and CMS experiments. The goals of the collaboration include the comprehensive understanding of radiation effects in the 65 nm technology, the development of tools and methodology to efficiently design large complex mixed signal chips and, ultimately, the development of a full size readout chip featuring a 400 × 400 pixel array with 50μm pitch. In August 2017, the collaboration submitted the large scale chip RD53A, integrating a matrix of 400 × 192 pixels and embodying three different analog front-end designs. This work discusses the characteristic of the RD53A chip, with some emphasis on the analog processors, and presents the first test results on the pixel array

RD53 analog front-end processors for the ATLAS and CMS experiments at the high-luminosity LHC

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration. The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper

RD53 analog front-end processors for the ATLAS and CMS experiments at the high-luminosity LHC

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration. The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper